1. Field
Example embodiments relate generally to a semiconductor memory device and method thereof.
2. Description of the Related Art
Semiconductor memory devices may be manufactured through a series of steps, such as design and process of semiconductor circuits, chip tests or tests after packaging. After fabrication, chip tests or the tests after packaging may be used to test semiconductor memory devices. Then, the tested semiconductor memory devices may enter the market.
In a conventional parallel bit test, test pattern data may be written into a plurality of memory cells of a semiconductor memory device, and the written test pattern data may be read. The read test pattern data and the written test pattern data may be compared to generate a comparison result, and a logic level of the comparison result may indicate whether a given tested semiconductor memory device may be functioning normally.
For example, the same data may be written in two memory cells among four memory cells. The two read data, which may be output from the memory cells having the same data written thereto, may be compared with each other, and a determination may be made as to whether the memory cells are normal based on the comparison result (e.g., if the comparison result for each respective memory cell is the same, normal operation may be determined, else bad or erroneous operation may be determined). For example, 4-bit data may be compared to generate one test result data, and if it is determined that the test result data indicates that the memory cells are defective, the four “defective” memory cells may be replaced with redundant memory cells. However, because the same data may be written into the memory cells to be compared, the formatting of the test pattern data may be relatively limited.
In another conventional parallel bit test process, “expected” data may be used. According to this process, expected data, which may correspond to the test pattern data written into a plurality of memory cells, may be input during a read operation. The expected data may be compared with read data, which may be read from the memory cells. Logic levels of the comparison results may be analyzed, and a determination may be made as to whether the memory cells are normal or defective. For example, 4-bit expected data, which may correspond to 4-bit data written into four memory cells, may be input again during a read operation. The 4-bit expected data may be compared with 4-bit read data so as to generate one test result data, and if the test result data indicates that the memory cells are defective, the four memory cells may be replaced with redundant memory cells.
However, in a conventional parallel bit test process, because the expected data may be input through a data bus (or data input/output pad) during a read operation, a read burst operation may not be performed. A read burst operation may correspond to consecutive or sequential read operations which may be performed repeatedly (e.g., without pauses or wait-states).
FIGS. 1A and 1B are timing diagrams illustrating a conventional parallel bit process.
Referring to FIG. 1A, at time t1, a first read command may be input at a rising edge of a clock, and expected data may be input through a data input/output pad together with the first read command. Test result data may be output for a given period of time (e.g., a time) after a given time interval tAA (hereinafter, referred to as “test result data output time). Here, tAA+α may be larger than a clock cycle tCC. Therefore, at time t2, a second read command may not be input at the rising edge of the clock because test result data being output and expected data, which may be input together with the second read command, may collide with each other because the same data bus is being used. Therefore, in order to perform the read burst operation, as shown in FIG. 1B, the clock period tCC may be configured to be larger than tAA+α, which may increase the clock cycle tCC, and may reduce an operating speed of the semiconductor memory device.